The trend of digitizing analog functionality often leads to time domain signal processing. In all-digital phase locked loops (PLL) for instance, the phase is quantized by means of time interval measurement. In a linear time-to-digital converter (TDC), the conversion of a time interval into a digital code may be started by one input signal and stopped by the other input signal. As this generally means that the start signal precedes the stop signal, a linear TDC (e.g., 102 at FIG. 1) is arranged to measure positive time intervals (e.g., asymmetrically). In a delay line-based TDC, for example, the start signal is fed into a delay line and propagates through delay elements, while the stop signal triggers the components that sample the state of the delay elements, ensuring that the start signal arrives before the stop signal. An example asymmetric output of a linear TDC is shown in FIG. 1 at diagram a).
Asymmetry has disadvantages, for example when a linear TDC 102 may be used in a feedback system where the average time interval to be measured is zero, and the TDC 102 needs to measure both positive and negative time values. For example, a measurement of bipolar time intervals, such as shown in FIG. 1 at diagram b) may be desired.
Signed or bipolar time interval measurement means that either of the two signal edges which define the time interval to be measured can lead. In conventional TDCs 102, however, the temporal sequence of the start and the stop signal may be well defined and fixed. This means that one signal starts the measurement and the other one stops the measurement. In the PLL application, a bipolar time interval measurement is desirable since the divided local oscillator (LO) signal edge, for example, can either lead or lag the reference signal.
To use a linear TDC 102 in a DPLL, for example, one solution is to delay the feedback signal with respect to the reference signal by a constant time offset, thereby guaranteeing that only positive phase-error values need to be measured. However, operating a DPLL with a positive offset results in increased TDC noise and power consumption.
Other solutions include forming some variation of a bipolar TDC arrangement, capable of measuring positive and negative time intervals, as shown in FIGS. 1 and 2, for example. For instance, one solution includes an approach, as illustrated in FIG. 1, where a positive offset (“delay”) 104 is added to the signed time interval. In one case, the offset is larger than the maximum of the absolute negative value. Thus the time interval is always positive and a conventional TDC 102 can be used. One drawback is that the measurement time is prolonged by the offset. As noise accumulates during the measurement and scales with the number of delay elements in a square root manner, a larger measurement time results in more phase noise, and thus reduced effective resolution. Moreover, a longer measurement time means longer conversion time and thus higher power consumption.
Another solution includes using an edge selector 202 with the linear TDC 102 to determine the sign of the time interval to be measured, as shown in FIG. 2A, for example. A further solution includes using a pair of TDCs 204, one forward and one reverse, with each having half the length of a single linear TDC 102, as shown in FIG. 2B, for example. In the case of the pair of TDCs 204, the first TDC 204 measures the time interval between a first and a second input signal while the second TDC 204 measures the time interval between the second and the first input signal. The digital results of the two TDCs 204 may be subtracted in the digital domain to form the bipolar result. Compared to the previous approach the measurement time may be reduced which results in reduced phase noise. However, the use of two TDCs 204 results in an increase (e.g., by a factor of two) in area and power consumption. Another drawback includes strong matching requirements between the two TDCs 204.
One common problem in the implementation of a linear TDC 102 is the presence of an unknown delay offset (t_off in FIG. 3). Such an offset may be caused by imperfections in the analog implementation and by different propagation delays in the signal paths. Further, the delay offset may be highly susceptible to process, voltage, and temperature variations. Because of the delay offset, a positive digital output may be generated even though the STOP signal may be leading the START signal (negative time interval) as seen in FIG. 3 at diagrams a) and b). This results in a shift of the TDC characteristic by t_off as seen in FIG. 3 at diagram b).
One significant problem is that the unknown delay offset may cause the TDC 102 characteristic to be nonlinear, even though the linear TDC 102 itself has a linear characteristic (FIG. 3 at diagram c)). A TDC 102 with a nonlinear characteristic is disadvantageous in many applications, particularly in feedback systems where a nonlinear element inside the loop may cause instability or degrade the system performance.